PowerFET Lab/Calculators/RC Snubber Designer

Switching-node ringing analysis

RC Snubber Designer

Model measured ringing, estimate the equivalent parasitics, and find a practical RC candidate with visible equations and tradeoffs.

Local calculationFull cubic modelResidue responseConstraint optimizer

What it doesModels switching-node ringing and evaluates a series RC branch across a third-order equivalent network.

Measurements neededBus and peak voltage, ringing frequency, decay time, switching frequency, and an estimate of C_eq.

Validation boundaryThe result is a first-pass engineering candidate. Confirm voltage, pulse energy, temperature, and EMI on hardware.

Measured ringing

Enter the minimum information from the switching-node capture.

DC bus voltage User input Switching frequency User input Measured peak voltage MeasuredUsed to reconstruct the measured ringing and its spectrum, and to validate—not force—the equivalent-RLC peak. Ringing frequency MeasuredMeasure between successive ringing peaks—not the converter switching frequency. Decay time constant Measured Equivalent C_eq User estimate

Design constraints

Set the electrical target separately from the measured waveform.

Maximum allowable switching peak User inputMaximum switching-node voltage allowed by the design. The optimizer searches for the lowest-loss snubber that keeps the predicted peak at or below this value. Device VDS rating User input optionalOptional entered device rating for margin reporting. No automatic safety derating is applied.

Advanced settingsPWM timing, sweep bounds, numerical resolution, and model overrides

Operating point and candidate

Duty cycle %Used for periodic PWM and spectral analysis. It does not alter the isolated ringing model unless commutation physics is enabled. Deadtime nsUsed for switching timing. Peak magnitude is not deadtime-dependent in the current lumped-RLC model. Selected C_s pFInitial damping estimate; not assumed to be optimal.

Sweep and numerical controls

Minimum C_s pF Maximum C_s pF Sweep step pF Harmonic count Time-response plot points

Equivalent model source

Parasitic model

MeasuredUser inputAssumedDerivedRecommended

Live analysis is on. Every valid edit recomputes the full model automatically.

Reference values ready.

PowerFET Lab engineering report

RC Snubber Design Analysis

Equivalent lumped-model estimate. The operating point, assumptions, selected RC, and predicted results below must be validated against measured hardware before production use.

Operating point and measured inputs

Selected model and design constraints

Selected RC and predicted result

Damping and loss summary

Fast answer

Candidate and recommendation

Visible proof

Before vs after snubber

Auto zoom to ringing

Equivalent step response · shared axes

Timing view

Periodic PWM waveform (3–5 cycles)

Displayed cycles

Auto zoom to ringing

Shows the selected number of PWM cycles using the current ringing model so duty cycle and deadtime affect timing visibly. Highest displayed peak is detected automatically.

Before and after snubber · shared periodic time axis

Design tradeoff

Suppression benefit versus electrical cost

Overshoot reduction vs estimated loss

Marginal suppression efficiency

Detailed analysisExtracted equivalent parasitic RLCL_par, R_eq, Q, damping, and substituted calculations

Equivalent parasitic model—not a direct physical extraction of one PCB trace or component.

Detailed analysisSelected RC model, cubic poles, and dynamicsFull third-order solution; no second-order substitution

Pole locations

Characteristic polynomial and roots

Detailed analysisCapacitance sweepPeak, reduction, loss, resistance, Q, and ringing-frequency vectors

Peak voltage vs C_s

Overshoot reduction vs C_s

Estimated snubber loss vs C_s

R_s vs C_s

Post-snubber Q vs C_s

Ringing frequency vs C_s

Detailed analysisSwitching-node spectral analysisNumerical Fourier series; not an EMI compliance prediction

Full switching spectrum · amplitude

Ringing-only spectrum · amplitude

Full switching spectrum · dBV

Ringing-only spectrum · dBV

Model boundary

Assumptions and limitations

The switching-node network is represented by an equivalent lumped model; real PCB behavior can contain distributed and nonlinear parasitics.
C_eq may be estimated, so the derived L_par is an equivalent resonant inductance—not a directly measured trace inductance.
Average snubber loss uses two ½C·V² energy events per switching period, giving C·V²·f. It is independent of duty and deadtime in this first-order convention.
Deadtime currently shifts the modeled switching transition only. A future commutation model would require switching/load current, C_oss or Q_oss, diode Q_rr, gate timing, and a defined ZVS condition.
Fourier results describe the modeled switching node. They are not CISPR, FCC, or conducted-emissions compliance predictions.
Validate voltage, pulse energy, temperature, EMI, and component ratings on measured hardware before release.

Equations & methodology

Measured ringing

V_os = V_peak − V_bus V_ring(t) = V_bus + V_ose^−t/τcos(2πf_rt)

Equivalent RLC

α = 1/τ, ω_d = 2πf_r ω₀ = √(ω_d² + α²) L_par = 1/(ω₀²C_eq) R_eq = 2αL_par

Initial RC estimate and loss

R_s = √(L_par/C_s) E_event = ½C_sV_bus² N_events = 2 per switching period P_snub ≈ N_eventsE_eventf_sw = C_sV_bus²f_sw

PWM timing and Fourier series

T_s = 1/f_sw, T_on = DT_s C[0] = (1/T_s)∫₀^TsV_sw(t)dt C[n] = (1/T_s)∫₀^TsV_sw(t)e^−jn2πfswtdt A[n] = 2|C[n]| A_dBV[n] = 20log₁₀(A[n]/1 V)

Periodic PWM comparison window

T_plot = N_cyclesT_s 0 ≤ t_phase < t_d: V_sw = 0 t_d ≤ t_phase < DT_s: apply the before- or after-snubber edge response DT_s ≤ t_phase < T_s: V_sw = 0 V_pk,window = max(V_sw[k]); the first nearly equal maximum is reported

Full cubic characteristic equation

a₃s³ + a₂s² + a₁s + 1 = 0 a₃ = L_parC_eqR_sC_s a₂ = R_eqC_eqR_sC_s + L_par(C_eq + C_s) a₁ = R_sC_s + R_eq(C_eq + C_s)

Poles and residue response

H(s) = (1 + sR_sC_s)/(1 + a₁s + a₂s² + a₃s³) K_k = V_bus(1 + p_kR_sC_s)/(p_kD′(p_k)) V_step,new(t) = Re[V_bus + ΣK_ke^pkt]

Optimization and marginal efficiency

minimize P_snub(C_s) subject to V_pk(C_s) ≤ V_allow dRE/dC ≈ [RE(C+h) − RE(C−h)]/(2h) η(C) = (dRE/dC)/(V_bus²f_sw)