Manufacturer-backed · peer-reviewed context

Topology computations, examples, figures, and failure modes.

This guide explains what each calculator input means, how the first-pass equations are formed, and where a real converter can depart from the ideal model. Examples follow Formula → Substitute → Answer so the numbers can be checked by hand.

Source standard. Design claims are linked to official manufacturer application notes and original IEEE papers. All figures below are original explanatory diagrams—not copied publication figures. Equations are screening models; validate final hardware with device curves, simulation, thermal analysis, double-pulse testing, and safe laboratory measurements.

1. How to use this guide

Start with the power stage

Choose the topology, enter its electrical targets, then use the preset only as a known starting point. Check current ripple and device stress before believing any loss number.

Use the best switching data available

Measured E_on/E_off at comparable voltage, current, gate resistance, and temperature is preferable. Rise/fall-time estimates are useful when energy data is unavailable, but they are sensitive to parasitics and gate-drive conditions.

Close the thermal loop

R_DS(on) rises with junction temperature, which raises conduction loss again. Iterate loss → temperature → resistance until the result settles.

Treat warnings as investigation points

A warning is not a component approval. Check absolute maximum ratings, repetitive transient capability, SOA, magnetics saturation, capacitor ripple rating, creepage, clearance, and protection response.

2. Parameter map

The calculator exposes only the fields relevant to the selected topology. This map groups the quantities used across all modes.

Symbol / input	Meaning	Unit	Why it matters
V_IN, V_OUT	DC input and regulated output voltage	V	Set conversion ratio and voltage stress.
V_AC,rms, f_line	AC-line RMS voltage and line frequency	V, Hz	PFC only: line peak, current, and twice-line ripple.
I_OUT, P_OUT	Load current and delivered power	A, W	Determine average device and magnetic current.
η, PF	Assumed efficiency and input power factor	ratio	Translate output power to realistic input current.
D, t_on, f_s	Duty ratio, on-time, switching frequency	ratio, s, Hz	Set conduction share, energy per cycle, ripple, and switching events.
L, ΔI_L	Inductance and peak-to-peak current ripple	H, A	Set CCM/DCM boundary, peak current, RMS current, and saturation risk.
C, ESR, I_ripple	Capacitance, series resistance, capacitor ripple current	F, Ω, A	Set output ripple, heating, and lifetime stress.
R_DS(on),25, α_R	MOSFET on-resistance at 25 °C and temperature coefficient	Ω, 1/°C	Drive conduction loss and thermal feedback.
t_r, t_f	Drain-voltage/current overlap transition times	s	Enable a simple hard-switching overlap estimate.
E_on, E_off	Measured switching energies for one event	J	Preferred switching-loss input when test conditions match.
Q_g, Q_gd, V_GP	Total gate charge, Miller charge, plateau voltage	C, C, V	Set driver power and estimated transition time.
R_g,int/ext, I_source/sink	Gate resistance or driver current capability	Ω, A	Control switching speed, ringing, overshoot, and false turn-on margin.
C_oss, E_oss	Output capacitance or stored output energy	F, J	Contribute to node-transition energy; strongly voltage-dependent.
Q_rr	Body-diode/recovery charge	C	Adds commutation energy and peak current.
t_d, V_F	Dead time and conducting-diode forward drop	s, V	Too short risks shoot-through; too long raises diode loss.
T_A, T_C, R_θ	Ambient/case temperature and thermal resistance	°C, °C/W	Convert device loss to estimated junction temperature.
L_r, C_r, L_m	Series resonant L/C and transformer magnetizing inductance	H, F, H	Set LLC/CLLC resonances, gain, circulating current, and ZVS range.
n, L_n, Q_e	Turns ratio, L_m/L_r, normalized load quality factor	ratio	Shape the resonant gain curve and load dependence.
V_margin, I_margin	Design headroom above predicted stress	%	Allows for tolerance, transient, ringing, and measurement uncertainty.

Datasheet conditions matter: a quoted 5 mΩ at 10 V gate drive and 25 °C is not automatically valid at 6 V gate drive and 125 °C. Use curves or a conservative measured value at the actual operating point.

3. Core electrical and loss models

Power and RMS current

P_OUT = V_OUT · I_OUT I_RMS,ramp = √(I_AVG² + ΔI_pp² / 12)

RMS—not average current—sets resistive heating. The second expression is for a triangular ripple centered on the average.

Temperature-adjusted conduction

R_DS(on)(T_J) ≈ R_DS(on),25[1 + α_R(T_J − 25)] P_cond = I_FET,RMS² · R_DS(on)(T_J)

The linear coefficient is a convenience. A normalized on-resistance curve from the selected device is better.

Switching overlap

P_sw ≈ ½V_DSI_D(t_r + t_f)f_s P_sw = (E_on + E_off)f_s

Use one method—not both for the same overlap energy. Energy curves or double-pulse measurements capture more real behavior than the linear overlap model.

Gate, output-capacitance, and recovery

P_gate = Q_gV_drivef_s P_oss ≈ ½C_ossV_DS²f_s P_rr ≈ Q_rrV_DSf_s

Prefer E_oss/Q_oss curves because C_oss is nonlinear. Avoid counting the same energy twice if the switching-energy data already includes it.

Dead-time diode conduction

P_dead ≈ V_FI_comm(2t_df_s)

The factor of two assumes two dead-time intervals per complete switching period. Confirm the actual commutation sequence.

Thermal screening

T_J ≈ T_A + P_lossR_θJA or T_J ≈ T_C + P_lossR_θJC

Do not mix case-referenced and ambient-referenced paths. PCB copper, airflow, interface materials, and neighboring heat sources change the effective resistance.

Figure 1 · What makes each loss term grow?

Conduction

∝ I_RMS² · R

Overlap switching

∝ V · I · t · f_s

Gate drive

∝ Q_g · V_g · f_s

Dead time

∝ V_F · I · t_d · f_s

Qualitative sensitivity figure. Bar lengths are not percentages and do not compare absolute losses.

Manufacturer derivations and loss categories: TI, synchronous-buck efficiency calculation, TI, power loss with common-source inductance, and TI, boost-converter design example. Research extensions include MOSFET switching-loss modeling (IEEE), datasheet-driven SiC switching prediction (IEEE), and temperature-dependent SiC reverse-recovery modeling (IEEE).

4. PWM switch and fully-on MOSFET

Manual PWM switch

One switched FETUser-set dutyHard-switching estimate

Figure 2 · Generic PWM energy path

DC source

→

Q1 · PWM

→

Load / power stage

Use this mode when the surrounding converter does not match a built-in topology and you already know the FET voltage, current, duty, and switching conditions.

Key computation

I_FET,RMS = I · √D P_cond = I²D · R_DS(on)

Worked example

Given

I = 10 A, D = 0.50, R_DS(on) = 5 mΩ

Substitute

P_cond = (10 A)²(0.50)(0.005 Ω)

Answer

P_cond = 0.250 W

Important details and likely failure causes

Wrong current shape: the √D shortcut assumes constant current during on-time; use waveform RMS for triangular or resonant current.
Avalanche or excessive V_DS: leakage inductance and layout can create turn-off overshoot.
Gate overstress or false turn-on: Miller current and source inductance change the real gate voltage.

Fully-on MOSFET

Static switchConduction dominated

Key computation

D = 1 I_FET,RMS = I P_cond = I²R_DS(on)

Worked example

Given

I = 10 A, R_DS(on) = 5 mΩ

Substitute

P_cond = (10 A)²(0.005 Ω)

Answer

P_cond = 0.500 W

Insufficient gate voltage: the device can sit in its linear region and overheat.
Hot-plug SOA violation: charging a large capacitor can impose high V_DS and I_D together.
Thermal runaway: higher junction temperature raises R_DS(on) and conduction loss.

5. Buck converter

Asynchronous or synchronous step-down

V_OUT < V_INCCM / DCMInductor output

Figure 3 · Buck power flow and labeled switches

V_IN

→

Q_HS
main PWM

→

L + C
energy filter

→

Load

In a synchronous buck, Q_LS replaces the catch diode and conducts for approximately 1 − D, excluding dead time.

CCM equations

D ≈ V_OUT / V_IN ΔI_L,pp = (V_IN − V_OUT)D / (Lf_s) I_L,RMS = √(I_OUT² + ΔI_L,pp²/12) I_HS,RMS ≈ I_L,RMS√D I_LS,RMS ≈ I_L,RMS√(1 − D)

Worked example: 48 V → 12 V

Given

V_IN=48 V, V_OUT=12 V, I_OUT=10 A L=100 µH, f_s=100 kHz

Duty

D = 12 / 48 = 0.25

Ripple

ΔI_L,pp = (48−12)(0.25)/(100 µH·100 kHz)

Answer

D = 25.0% · ΔI_L,pp = 0.900 A I_L,RMS = 10.003 A

CCM/DCM boundary: the ideal triangular inductor current reaches zero when I_OUT = ΔI_L,pp/2. Below that load the converter enters DCM and the simple duty relationship changes.

Failure causes to investigate

Inductor saturation: I_peak = I_OUT + ΔI/2 can exceed the core’s temperature-dependent limit.
Shoot-through: Q_HS and Q_LS overlap because dead time is too short or Miller turn-on occurs.
Excess diode loss: dead time is too long, so the body diode carries load current unnecessarily.
Output ripple/heating: insufficient effective capacitance, high ESR, or capacitor ripple-current rating exceeded.

See TI’s synchronous-buck efficiency method, TI’s dead-time analysis, and IEEE analysis of common-source inductance and Kelvin source connection.

6. Boost and synchronous boost

Boost converter

V_OUT > V_INInput inductorHigh switch current

Figure 4 · Boost energy path

V_IN

→

L
stores energy

↗

Q_MAIN
charges L

↘

D / Q_SR + C_OUT

→

Load

Q_MAIN pulls the switching node low during D. The diode or synchronous rectifier transfers inductor energy to the output during 1 − D.

CCM equations

D ≈ 1 − V_IN/V_OUT I_IN ≈ P_OUT/(ηV_IN) ΔI_L,pp = V_IND/(Lf_s) I_MAIN,RMS ≈ I_L,RMS√D I_RECT,RMS ≈ I_L,RMS√(1−D)

Worked example: 24 V → 48 V

Given

V_IN=24 V, V_OUT=48 V, I_OUT=5 A η=100% (ideal ripple example), L=100 µH, f_s=100 kHz

Substitute

D=1−24/48=0.50 I_IN=(48·5)/24=10 A ΔI=24·0.50/(100 µH·100 kHz)

Answer

D = 50.0% · I_IN = 10.0 A · ΔI_L,pp = 1.20 A

Excess switch voltage: Q_MAIN normally blocks about V_OUT plus overshoot.
Inductor saturation: input current can be much larger than output current at high conversion ratio.
Output overshoot: load removal leaves stored inductor energy that must be controlled.
Diode recovery loss: reverse recovery can raise turn-on current and EMI.

Design and loss context: TI AN-1696 boost design example and IEEE datasheet-based MOSFET/diode half-bridge loss model.

Synchronous boost

Q_MAIN + Q_SRAutomatic complementary on-timeDead-time sensitive

Timing model

D_MAIN ≈ 1 − V_IN/V_OUT D_SR,ideal ≈ 1 − D_MAIN D_SR,on ≈ max[0, 1 − D_MAIN − 2t_df_s] D_diode ≈ 2t_df_s

Worked timing example

Given

D_MAIN=0.50, f_s=100 kHz, t_d=100 ns

Substitute

D_SR,on=1−0.50−2(100 ns)(100 kHz)

Answer

D_SR,on=0.480 · body-diode share=0.020

Reverse current: forcing Q_SR on in DCM can pull energy backward unless the controller detects zero current.
Shoot-through: complementary commands alone do not guarantee safe non-overlap at the MOSFET pins.
Body-diode heating: excess dead time or slow gate transitions increase diode conduction.
False turn-on: high dV/dt couples through C_gd; layout and sink impedance matter.

Dead-time and Miller-coupling guidance: TI, configurable dead time and dV/dt turn-on and Infineon, parasitic-induced false turn-on.

7. Half bridge and full bridge

Half bridge

Q_HS + Q_LSSwitch nodeShoot-through risk

Figure 5 · Half-bridge switching leg

+V_BUS

→

Q_HS

⇄

SW node
load / transformer

⇄

Q_LS

→

0 V

Q_HS and Q_LS must never be intentionally on at the same time. Current may commutate through either body diode during dead time.

Constant-current screening

I_HS,RMS ≈ I√D I_LS,RMS ≈ I√(1−D) V_DS,rated > V_BUS + V_overshoot

Worked example

Given

I=8 A, D=0.50

Substitute

I_HS,RMS=I_LS,RMS=8√0.50

Answer

I_HS,RMS=I_LS,RMS=5.657 A

Cross-conduction: propagation-delay mismatch, inadequate dead time, or dv/dt false turn-on.
Bootstrap undervoltage: high-side gate supply cannot refresh during long on-time.
V_GS ringing: gate-loop and common-source inductance can exceed gate limits or retrigger the device.
Switch-node overshoot: power-loop inductance and abrupt current commutation create V = L·di/dt.

See TI’s detailed common-source-inductance loss analysis, Infineon’s V_GS ringing/layout guidance, and the corresponding IEEE device-switching study.

Full bridge

Four FETsBipolar primary voltageIsolated stages

Figure 6 · Full-bridge diagonal pairs

Q1 ↘
Q4 ↖

⇄

Transformer
primary

⇄

Q2 ↙
Q3 ↗

One diagonal applies +V_BUS; the other applies −V_BUS. The control sequence must preserve volt-second balance and avoid same-leg overlap.

First-pass current sharing

I_{PRI,AVG-equivalent} ≈ P_OUT/(ηV_IN) I_FET,RMS ≈ I_PRI/√2 P_cond,total ≈ 4I_FET,RMS²R_DS(on)

For a real transformer current waveform, calculate RMS over each device’s actual conduction interval.

Worked example

Given

P_OUT=1 kW, V_IN=400 V, η=95%

Substitute

I_PRI≈1000/(0.95·400)=2.632 A I_FET,RMS≈2.632/√2

Answer

I_FET,RMS≈1.861 A per switch (simplified)

Flux walking: unequal positive and negative volt-seconds create transformer DC bias and saturation.
Wrong diagonal timing: logic or driver faults short the bus.
Leakage overshoot: transformer leakage and layout energy stress the FETs at turn-off.
Insulation breakdown: creepage, clearance, partial discharge, and transformer interwinding stress require a dedicated safety design.

For transformer loss and insulation context, see IEEE Transactions on Power Electronics: high-frequency transformer design with medium-voltage insulation.

8. LLC resonant converter

LLC tank design screen

L_r + C_r + L_mFrequency controlZVS target

Figure 7 · LLC resonant energy path

Half/full
bridge

→

L_r + C_r
series tank

→

Transformer
L_m, ratio n

→

Rectifier / SR

→

C_OUT + load

The tank’s impedance changes with switching frequency. Operation near series resonance often minimizes circulating current, while the required gain range determines operation above and below resonance.

Core normalized parameters

f_r = 1/[2π√(L_rC_r)] Z_r = √(L_r/C_r) L_n = L_m/L_r Q_e = Z_r/R_e M_req = nV_OUT/V_IN (calculator convention)

Definitions for R_e, n, and gain depend on whether the primary is half bridge or full bridge and on the rectifier/load reflection convention. Keep one convention throughout the design.

Worked tank example

Given

L_r=40 µH, C_r=63.3 nF, L_m=200 µH

Substitute

f_r=1/[2π√(40 µH·63.3 nF)] L_n=200/40

Answer

f_r≈100.0 kHz · L_n=5.00

Design sequence

Define minimum/maximum input voltage, output range, overload, hold-up, and regulation limits.
Select transformer ratio so nominal operation stays near unity tank gain.
Choose f_r, L_n, and Q_e; plot gain across input, load, and component tolerances.
Check that the operating trajectory stays in the intended inductive/ZVS region.
Calculate tank RMS/peak current, capacitor voltage, magnetizing current, core loss, winding loss, and rectifier/SR loss.
Verify startup, short circuit, burst/light load, dead time, and control-frequency limits.

Loss of ZVS: insufficient magnetizing/tank current cannot discharge the bridge C_oss during dead time.
Excess circulating current: poor L_n/Q selection or operating far from resonance raises copper and FET conduction loss.
Capacitive-region operation: can cause hard commutation and severe switching stress.
Transformer saturation: startup, asymmetrical drive, or excessive magnetizing current violates flux limits.
Resonant-capacitor overstress: high RMS current and tank voltage cause heating or dielectric failure.

Primary sources: TI LLC design procedure for UCC29950, TI explanation of LLC gain, Q, and L_n, and A Complete Step-by-Step Optimal Design for LLC Resonant Converter (IEEE).

9. Bidirectional CLLC

CLLC resonant tank

BidirectionalTwo active bridgesFive tank elementsTolerance sensitive

Figure 8 · Symmetrical CLLC path

Primary
active bridge

⇄

L_r1 + C_r1

⇄

Transformer
L_m, n

⇄

L_r2 + C_r2

⇄

Secondary
active bridge

With a symmetrical referred tank, forward and reverse operation can have similar resonant behavior. The physical secondary parameters must be referred consistently through n.

Resonance and matching screen

f_r1 = 1/[2π√(L_r1C_r1)] f_r2 = 1/[2π√(L_r2C_r2)] L′_r2 = n²L_r2 C′_r2 = C_r2/n² Screening target: f_r1 ≈ f′_r2

Prime marks denote quantities referred to the chosen side. Confirm how your turns ratio n is defined before applying n².

Worked resonance example

Given

L_r1=30 µH, C_r1=84.4 nF L′_r2=30 µH, C′_r2=84.4 nF

Substitute

f_r=1/[2π√(30 µH·84.4 nF)]

Answer

f_r1≈f′_r2≈100.0 kHz

ZVS energy screen:

½L_commI_comm² ≥ ½C_eqV_bridge²

This necessary-energy check does not prove ZVS; nonlinear C_oss, dead time, magnetizing current, device capacitance, and the exact commutation path must be included.

Design sequence

Specify both power directions, voltage ranges, power levels, and startup/precharge states.
Select transformer ratio near the nominal DC conversion ratio.
Choose a tank symmetry/reference convention and solve forward and reverse gain surfaces.
Sweep L/C tolerance, magnetizing inductance, load, and dead time; identify ZVS boundaries.
Check all four bridge legs, both resonant capacitors, transformer, and controller transition states.

Forward/reverse mismatch: referred tank values or controller limits satisfy only one power direction.
Light-load hard switching: commutation current is too small to move both bridge-node capacitances.
Tank tolerance split: L/C drift separates the intended resonances and increases current.
Mode-transition surge: direction reversal without coordinated phase/frequency/current control causes excessive tank energy.
Capacitor or transformer overheating: high circulating RMS current is missed when only output power is considered.

Primary sources: TI’s bidirectional CLLLC topology application brief and Design Methodology of Bidirectional CLLC Resonant Converter (IEEE). For bidirectional transitions, see automatic forward/backward LLC transition (IEEE).

10. Totem-pole boost PFC

Single-phase bridgeless PFC

AC line onlyFast leg + line-frequency legCCM / CrM / DCMHazardous voltage

Figure 9 · Totem-pole PFC functional path

AC line
V_AC

→

Boost
inductor

→

Fast leg
Q_HF1/Q_HF2

Slow leg
Q_LF1/Q_LF2

→

HV DC bus
C_BUS

The slow leg changes with line polarity. The high-frequency leg shapes inductor current to follow the rectified line. Real implementations require line sensing, current control, protection, inrush limiting, and safe isolation.

First-pass equations

V_AC,pk = √2V_AC,rms I_line,rms ≈ P_OUT/(η·PF·V_AC,rms) D(θ) ≈ 1 − |v_AC(θ)|/V_BUS ΔI_L,pp(θ) ≈ |v_AC(θ)|D(θ)/(Lf_s) ΔV_BUS,pk ≈ P_OUT/(4πf_lineC_BUSV_BUS)

Worked line-current example

Given

P_OUT=1 kW, V_AC,rms=230 V, η=95%, PF=0.99

Substitute

I_line,rms=1000/(0.95·0.99·230)

Answer

V_AC,pk=325.3 V · I_line,rms≈4.624 A

Mode selection: CCM has lower peak current but hard-switching/recovery challenges. Critical/boundary conduction turns on near zero inductor current but varies frequency. DCM has an interval of zero current and higher peaks. The controller, EMI filter, magnetics, sensing, and loss model must match the selected mode.

Zero-crossing distortion: polarity handoff, dead time, minimum on-time, and current-sense offsets distort line current.
Fast-leg shoot-through: timing or Miller turn-on directly shorts the HV bus.
Reverse-recovery stress: a silicon MOSFET body diode in hard CCM commutation may produce prohibitive current and loss.
Bus overvoltage: load removal or control-loop error overcharges the output capacitor.
Inductor saturation: low-line peak current, startup, or fault current exceeds the magnetic design.
Unsafe construction: mains circuits require fusing, inrush control, isolation strategy, spacing, enclosure, and applicable compliance review.

Topology research: Totem-Pole Boost Bridgeless PFC at the Boundary of DCM/CCM (IEEE). General switching and recovery context: TI power-device switching-loss overview.

11. Input/output ripple and passive stress

Capacitor voltage ripple

v_ripple(t) = (1/C)∫i_C(t)dt + i_C(t)·ESR ΔV ≈ ΔQ/C + ΔI·ESR

The capacitive component follows charge balance; the ESR component changes immediately with capacitor current.

Capacitor heating

P_cap ≈ I_C,RMS²·ESR(f,T)

Use the ripple-current spectrum and frequency/temperature-dependent impedance, not only a DC ESR number.

Inductor copper

P_Cu ≈ I_L,RMS²·DCR(T) + P_{AC winding}

Skin and proximity effects raise winding resistance at switching frequency and harmonics.

Core loss

P_core = f(B, ΔB, waveform, material, volume, temperature)

Use manufacturer loss curves or a waveform-aware model for the actual core material. A single generic Steinmetz fit may be inaccurate for nonsinusoidal excitation.

Capacitor application caution: Murata’s polymer-capacitor design guidance. Magnetic modeling research: IEEE core-loss calculation method for DC/DC power converters.

12. Failure-analysis workflow

Figure 10 · From design cause to destructive failure

Root causeBad dead time, layout, cooling, sensing, or component selection

Electrical effectOverlap current, overshoot, ringing, saturation, or unstable control

Visible symptomHot device, noisy gate, distorted current, efficiency drop, resets

Accumulated stressExcess T_J, avalanche, gate oxide stress, capacitor heating

FailureShort/open FET, cracked capacitor, saturated core, insulation breakdown

Work from the waveform back toward the cause. A failed MOSFET is often the last event, not the original fault.

Electrical checks

V_DS, V_GS, I_D, switching energy, SOA, avalanche
Dead time at the device pins
Current-sense saturation/noise and fault delay
Magnetic peak flux/current and capacitor RMS current

Thermal checks

Worst-case ambient, airflow, interface, and PCB copper
Temperature-adjusted R_DS(on) and magnetics/capacitor limits
Transient thermal impedance for pulses
Thermocouple/IR measurement limits and calibration

Waveform checks

Use a differential probe with adequate common-mode rating
Use a short ground spring for low-side gate measurements
Separate Q_HS/Q_LS gate-source waveforms from driver-command signals
Correlate V_DS, I_D, V_GS, and switching-node timing

Protection checks

Cycle-by-cycle current limit and short-circuit response
UVLO/OVLO, output overvoltage, overtemperature
Precharge/inrush and safe discharge
Single-fault behavior and fuse/isolator coordination

Failure and protection references: TI short-circuit and shoot-through protection brief, TI dead-time optimization, and IEEE Open Journal thermal-management validation for high-power SiC MOSFETs.

13. Source library

Links point to the original publisher or manufacturer. Access to some IEEE full texts may depend on the reader’s institution; the abstract and bibliographic record remain useful for traceability.

Verified manufacturer material

TI · BuckAn Accurate Approach for Calculating the Efficiency of a Synchronous Buck Converter Using the MOSFET Plateau Voltage.
TI · LossPower Loss Calculation with Common Source Inductance Consideration for Synchronous Buck Converters.
TI · BoostAN-1696: Designing a Boost LED Driver Using the LM5022.
TI · LLCDesigning an LLC Resonant Half-Bridge Power Converter.
TI · LLCUnderstanding LLC Operation, Gain, Q, and L_n.
TI · CLLLCBidirectional CLLLC Resonant Converter Topology.
TI · TimingOptimizing Dead Time in Power Converter Designs.
TI · GateConfigurable Dead Time and dV/dt-Induced Turn-On.
InfineonExternal components and layout measures to reduce V_GS ringing.
MurataPolymer capacitor design and ripple-current cautions.

Peer-reviewed IEEE journal research

Each item below is identified by IEEE Xplore as a Journals & Magazine publication; conference-only papers are not used as the principal journal references in this guide.

Journal · MOSFETMOSFET Switching Loss Model and Optimal Design of a Current Source Driver Considering the Current Diversion Problem.
Journal · SiCAn Analytical Switching Loss Model for SiC MOSFET Considering Temperature-Dependent Reverse Recovery.
Journal · SiCDatasheet Driven Switching Loss, Overvoltage, di/dt, and dv/dt Prediction for SiC MOSFET.
Journal · LayoutSiC MOSFET Common Source Inductance and Kelvin Source Connection.
Journal · LLCA Complete Step-by-Step Optimal Design for LLC Resonant Converter.
Journal · CLLCDesign Methodology of Bidirectional CLLC Resonant Converter for High-Frequency Isolation.
Journal · PFCTotem-Pole Boost Bridgeless PFC Rectifier at the Boundary of DCM/CCM.
Journal · MagneticsA Core Loss Calculation Method for DC/DC Power Converters Based on Sinusoidal Losses.
Journal · ThermalThermal Management and Experimental Validation of a Copper-Inlay PCB for SiC MOSFETs.

Safety and model limitation

This guide is educational and intended for early design screening. It does not certify component suitability, product safety, EMC, insulation, reliability, or regulatory compliance. Mains and high-energy converters can cause fire, electric shock, arc flash, and equipment damage. Use qualified supervision, appropriate probes and PPE, current-limited sources, isolation where required, and a formal design review.

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