Power Device & Converter Loss Calculator
Configure a converter, quantify semiconductor loss, and review thermal and rating margin.
LOCAL-FIRST · NO UPLOADS
What it doesModels per-device and converter loss across twelve standard power topologies.
What it needsAn operating point, device data, switching method, and thermal assumptions.
Model boundarySteady-state screening model. Confirm dynamic stress, SOA, and temperature on hardware.
Fast answer · Synchronous buck
Steady-state converter analysis
Enter a generic design operating point, then calculate. All inputs and results remain in this browser session.
Analysis stateREADYReview inputs, then calculate.
Resolved mode—
Output power—
Design check—
Model consistency
Isolated PWM operating point
Investigating leakage-related drain spikes? Open RC Snubber Designer. Validate the appropriate clamp strategy for this isolated topology.
Detailed analysis
Power-device results
| Device | Duty | Ipk | Irms | Pcond | Psw | Gate (system) | Tj | Die loss | Check |
|---|
Loss breakdown
Where the power goes
Advanced analysis
Explore sensitivity and device tradeoffs
Visible proof
Topology schematic
Synchronous buck · labeled semiconductor map
Click a FET label to highlight its calculated row.
Functional power-stage diagram only — not a gate-drive, protection, or PCB-layout schematic.
CLLC resonant-tank design
FHA sizing, bidirectional gain coverage and ZVS screeningSelect CLLC and calculate to generate the resonant-tank design.
Visible proof
Calculated waveforms
Ten steady-state switching cycles
Idealized engineering waveforms; parasitic ringing is not simulated.
—
How it works
From operating point to an explainable loss estimate
PowerFET Lab uses standard steady-state converter relationships and user-entered datasheet parameters. It keeps conduction, switching, gate-drive, body-diode, ripple, passive, and thermal estimates visible so each result can be reviewed instead of treated as a black box.
01 · DEFINE
Select the power stage
Choose a recognized converter topology and enter the electrical operating point.
02 · MODEL
Enter component data
Use public MOSFET datasheet values, passive values, switching frequency, and thermal assumptions.
03 · REVIEW
Inspect every result
Compare per-device loss, junction temperature, ripple, waveforms, equations, and design margins.
Topology directory
Standard power-converter stages covered by the calculator
All descriptions and default values are generic educational examples. The calculator contains no company designs, proprietary component databases, customer records, or uploaded documents.
General
PWM
Manual PWM switch
A single switch with user-defined voltage, current, duty cycle, and switching conditions.
DC
Fully-on MOSFET
A continuous-current pass FET model focused on resistance and temperature-dependent conduction loss.
Non-isolated PWM
BUCK
Synchronous buck
A step-down stage with high-side and synchronous low-side MOSFETs.
BOOST
Boost converter
A step-up stage using an inductor, main MOSFET, diode rectifier, and output capacitor.
S-BOOST
Synchronous boost
A boost stage with an actively controlled MOSFET replacing the output rectifier diode.
Isolated PWM
FLY
Flyback
An isolated stored-energy stage with explicit magnetizing current, reflected voltage, and CCM/DCM timing.
FWD
Single-switch Forward
An isolated on-time energy-transfer stage with an output inductor and reset-winding validation.
HB
Half bridge
Two complementary MOSFETs that create a switching midpoint from a DC bus.
FB
Full-bridge PWM
Four switches generating a bipolar differential voltage across a transformer or load.
Resonant
LLC
Full-bridge LLC
A resonant full bridge using an Lr–Cr tank and transformer magnetizing inductance.
CLLC
Dual full-bridge CLLC
A bidirectional isolated resonant stage with primary and secondary active bridges.
AC/DC
PFC
Totem-pole PFC
A bridgeless boost power-factor-correction stage with high- and line-frequency legs.
Independent reference checks
Textbook equations checked against the calculator engine
These simplified cases intentionally disable secondary dynamic effects so a key result can be reproduced directly from the displayed equation. They are separate from the broader topology model regression suite.
PASS means every displayed calculator value is within the stated numerical tolerance of the independently evaluated reference equation. Hardware accuracy still depends on datasheet and measurement quality.
Responsible use
A design-screening tool, not a replacement for validation
Results depend on the entered data and simplified models. Before hardware release, check nonlinear capacitance and switching-energy curves, temperature-dependent parameters, magnetic behavior, SOA, transient thermal impedance, control stability, parasitic ringing, PCB layout, protection behavior, and measured waveforms.